ADM1041-EVAL【PDF 35/64 页】BOARD EVALUATION ADM1041

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Sheet目录17367

31页 32页 33页 34页 [35页]36页 37页 38页 39页

ADM1041

19

9

1

9

SCLK

SDATA

A6

A5

A4

A3

A2

A1

A0

R/W

D7

D6

D5

D4

D3

D2

D1

D0

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

SCLK (CONTINUED)

ACK. BY

ADM1041

1

FRAME 2

ADDRESS POINTER REGISTER BYTE

9

ACK. BY

ADM1041

SDATA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

ADM1041

STOP BY

MASTER

FRAME 3

DATA BYTE

Figure 25. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

1

9

1

9

SCLK

SDATA

A6

A5

A4

A3

A2

A1

A0

R/W

D7

D6

D5

D4

D3

D2

D1

D0

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK. BY

ADM1041

FRAME 2

ADDRESS POINTER REGISTER BYTE

ACK. BY

ADM1041

STOP BY

MASTER

Figure 26. Writing to the Address Pointer Register Only

1

9

1

9

SCLK

SDATA

A6

A5

A4

A3

A2

A1

A0

R/W

D7

D6

D5

D4

D3

D2

D1

D0

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK. BY

ADM1041

FRAME 2

DATA BYTE FROM ADM1041

ACK. BY

ADM1041

STOP BY

MASTER

Figure 27. Reading Data from a Previously Selected Register

Table 6. Device SMBus Addresses

ADD1

0

0

0

1

1

1

ADD0

GND

V DD

NC

GND

V DD

NC

A2

0

0

1

0

0

1

A1

0

0

0

1

1

0

A0

0

1

0

0

1

1

Target Device

0

1

4

2

3

5

Note: ADD1 is low by default. To access the additional three addresses it is necessary to set Config 4 < 1 > high and then perform a power cycle to allow the new

address to be latched after the EEPROM download. Refer to the section on Extended SMBUS Addressing for more details.

Rev. A | Page 35 of 64

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